`timescale 1ns/100ps

module accTest;

 reg [3:0] IN;
 reg CLK, RST;
 wire [3:0] OUT;

 acc myAcc (.CLK(CLK), .RST(RST), .IN(IN), .OUT(OUT));

 initial
  begin
   CLK=1'b0;
   repeat (40)
    #5 CLK = ~CLK;
  end

 initial
  begin
   #0 RST=1'b1; IN=4'b0001;
   #10 RST=1'b0;
   #90 RST=1'b1;
  end

 initial
  $monitor("time=%0d: OUT=%1h", $time, OUT);

 initial
  begin
   $dumpfile("test.lxt");
   $dumpvars(0,accTest);
  end

endmodule // accTest

