`timescale 1ns/1ps

// Behavioral model of 4-bit Register:
// positive edge-triggered,
// synchrounous active-high reset.

module reg4 (CLK,Q,D,RST);
 input [3:0] D;
 input CLK, RST;
 output [3:0] Q;
 reg [3:0] Q;

 always @ (posedge CLK)
  if (RST) #1 Q = 0; else #1 Q = D;

endmodule // reg4
