LOADMEM # test 1
zero r1        # 0
ori r1 64      # 1
cp r3 r1       # 2
jal 5          # 3 jump to 4, skip one instruction
cp r2 r1       # 4 should not be executed
ori r2 1       # 5
jr r2 7        # 6 jump to 1+7, skip one instruction
add r2 r1 r2   # 7 should not be executed
ori r4 4       # 8
sub r4 r4 r2   # 9 r4 -= 1
brnz r4 -2     # 10 branch to 9 as long as r4!=0
sw r3 r1 5     # 11 store 64 in DATA[64+5]
lw r5 r1 5     # 12 load DATA[64+5] (4) in r6
lw r3 r1 4     # 13 load DATA[64+4] (0) in r3
j 20           # 14
CHECKMEM
r1: 64
r2: 1
r3: 0
r4: 0
r5: 64
r15: 4
pc: 20
END

LOADMEM # test 2
zero r1
lui r1 1
CHECKMEM
r1: 256
r2: 0
r3: 0
r15: 0
END

LOADMEM # test 3
zero r1
ori r1 1
CHECKMEM
r1: 1
r2: 0
r3: 0
r15: 0
END

LOADMEM # test 4
zero r1
jal 25
CHECKMEM
pc: 25
r15: 2
END

LOADMEM # test 5
zero r1       # 0
ori r2 1      # 1
jal 6         # 2
ori r3 2      # 3
eq r1 r2 r3   # 4
brnz r1 2     # 5
add r2 r2 r2  # 6
jr r15 0      # 7
jal 25        # 8
CHECKMEM
pc: 25
r1: 1
r2: 2
r3: 2
r15: 9
END

LOADMEM # test 6
zero r1
ori r1 20
jr r1 5
CHECKMEM
pc: 25
END

LOADMEM # test 7
zero r1
ori r1 20
jr r1 -5
CHECKMEM
pc: 15
END

LOADMEM # test 8
zero r1
brnz r0 4 # should not branch
CHECKMEM
pc: 2
END

LOADMEM # test 9
zero r1
ori r1 1
brnz r1 3 # should branch (pc+1+3=6)
CHECKMEM
pc: 6
END

LOADMEM # test 10
zero r1
ori r2 1
lw r1 r2 3
DATAMEM
100
CHECKMEM
r1: 100
r2: 1
END

LOADMEM # test 11
zero r1
ori r1 25
sw r1 r0 6
lw r2 r0 6
CHECKMEM
r1: 25
r2: 25
END

LOADMEM # test 12
zero r1
ori r1 1
ori r2 4
sub r2 r2 r1
brnz r2 -2
j 25
CHECKMEM
pc: 25
r1: 1
r2: 0
END