LOADMEM
zero r3 # 0 instruction that is actually used as immediate...
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 1
LOADMEM
ldi r2 7
CHECKMEM
r0: 0
r1: 0
r2: 7
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 2
LOADMEM
gt r3 r2 r1 # 2 test gt
CHECKMEM
r0: 0
r1: 0
r2: 7
r3: 1
r4: 0
r5: 0
r6: 0
r7: 0
pc: 3
LOADMEM
gt r2 r1 r3 # 3 test gt
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 1
r4: 0
r5: 0
r6: 0
r7: 0
pc: 4
LOADMEM
gt r3 r0 r0 # 4 test gt
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 5
DATAMEM # 5
7 # 6
END

LOADMEM
zero r3 # 0 instruction that is actually used as immediate...
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 1
LOADMEM
ldi r2 7
CHECKMEM
r0: 0
r1: 0
r2: 7
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 2
LOADMEM
lt r3 r1 r2 # 2 test lt
CHECKMEM
r0: 0
r1: 0
r2: 7
r3: 1
r4: 0
r5: 0
r6: 0
r7: 0
pc: 3
LOADMEM
lt r2 r3 r1 # 3 test lt
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 1
r4: 0
r5: 0
r6: 0
r7: 0
pc: 4
LOADMEM
lt r3 r0 r0 # 4 test lt
CHECKMEM
r0: 0
r1: 0
r2: 0
r3: 0
r4: 0
r5: 0
r6: 0
r7: 0
pc: 5
DATAMEM # 5
7 # 6
END
