- Team:
Farah Fariz
ffariz@cs.mcgill.ca
Victor Isaias Cano Becerril
victor.canobecerril@mail.mcgill.ca
- Motivation:
Testing a processor before releasing it is vital especially since this processor will be used in various fields which include hospitals,
banks, universities and so on. This means the processor must be robust and must work properly before being released to the public. This
project concentrates on producing a simulation of a simple 8-bit processor with a few simple mips instructions. Yet it must be noticed
that although the scale is minuscule compared with the processors we use today, it gives us insight on how everything works together
and how things can be improved and helps detecting vital mistakes.
- Proposal/Requirements:
In this project we will be using Logisim to create an 8-bit single cycle CPU.
ISA
We will be implementing a simple 8-bit processor with only two registers ($r0 and $r1). It will have separate data and instruction memory.
The instruction encoding is given below. We determine which instruction a byte encodes by looking at the opcode (the top three bits).
srl vs. sra
Just as in MIPS, srl and sra differ here by sign extension. Since sra stands for shift right arithmetic, it considers it's operand
a two's complement signed number and sign extends appropriately. srl considers it's operand a set of separate logical values, and
zero extends instead.
jump
The jump instruction's argument is a pseudoabsolute address, just as in MIPS. address is an unsigned number representing the lower
five bits of the next instruction to be executed. The upper three bits are taken from the current PC.
PC = (PC & 0xe0) | address
beq
The beq instruction's argument is a signed offset relative to the next instruction to be executed normally, also as in MIPS. beq
can be represented as the following:
if $r0 == $r1
PC = PC + 1 + offset
else
PC = PC + 1
immediate Fields
All immediate fields are treated as unsigned numbers and are zero-extended accordingly.
- Design/Models:
Every computer has five parts: control, datapath, memory, input, and output devices.
Control:
Datapath:
- Instruction Fetch
- Decode instructions and Execution
This is done within the ALU, and it's built like this:
- Write back to registers
For this we built a register file, which is built like this:
- Write back to memory
For memory used a prebuilt RAM file from the logisim library.
Memory:
For memory we used the built-in memory library, (to add it, click on "Project/Load Library/Built-in Library..."
and then select the Memory module).
"A" chooses which address will be accessed (if any). "sel" essentially determines whether or not the RAM module is active (if "sel"
is low, "D" is undefined). The clock input provides synchronization for memory writes. "out" determines whether or not memory is
being read or written. If "out" is high, then "D" will be driven with the contents of memory at address "A". "clr" will instantly
set all contents of memory to 0 if high. "D" acts as both data in and data out for this module. The "poke" tool can be used to
modify the contents of the module.
Input:
Used built in input for a 256B ROM
Output:
Our project includes an array of four seven-segment
displays for output.
The disp instruction assigns a register's value to the immth seven-segment display. This value is held until the next time a disp
instruction replaces that display index. A converter library to make seven-segment displays easier to deal with is provided, it can
be downloaded here and is included via
the "Load Library/Logisim Library" menu option. Any single digit hexadecimal value 0-f will be displayed as we'd expect.
So, here's everything put together:
- Implementation:
The file containing logisim can be downloaded here.
The file containing the display for logisim can be downloaded here.
The file containing the assembler can be downloaded here.
The file containing our implementation can be downloaded here.
- Experiments:
Testing
Once we implemented our CPU, we test it's correctness by writing a program to run on it. A simple loop that increments by one is written.
Assembler
A simple assembler is provided to make writing programs easier.
The assembler can be downloaded here. The assembler takes files of the following form:
lui $r0, 3
ori $r0, 15
lui $r1, 3
ori $r1, 15
beq -1
Anywhere a register is required, it must be either $r0 or $r1. Labels are not supported and immediates are decimal and not checked for being within bounds.
Any blank lines or malformed instructions will correspond to a nop in the executable. The assembler can be invoked using the following UNIX command:
% perl asm.pl output.hex
A simple example of an adder which increments by 1 every step and displays the output is the following:
lui $r1, 1
srl $r1, $r1
srl $r1, $r1
srl $r1, $r1
srl $r1, $r1
add $r0, $r1
disp $r0, 0
jump 5
using the perl assembler we get :
51
1c
1c
1c
1c
b
20
c5
and placing that in the input to the CPU we get the desired result.
- Conclusions:
The simulation that was implemented can be expanded for more commands with what is available in mips.
Also it might be expanded to the current processors yet the testing and implementation will be on a
larger more elaborate scale. This can be used to test the reliability of a processor and test how much
memory is required for certain commands and how memory is altered by each.
In addition new models of processors can be tested before being sent to the market to see how they
perform. This is an ideal way to make sure a processor is sufficiently robust and thus an important
part of processor testing, in addition to physical testing which comes after.Also this can be used to
test assemblers and compilers for different programming languages.
- References:
reference book:
Computer Organization and Design: The Hardware/Software interface
Authors:
David A. Patterson
John L. Hennessy
Publisher: Morgan Kaufmann; 3 edition (June 1, 2007)
ISBN-10: 0123706068
ISBN-13: 978-0123706065
Website:
http://inst.eecs.berkeley.edu/~cs61c/fa06/assignments/proj/3/
- Presentation:
The file for our presentation can be downloaded here.
- Who did what:
Victor: ALU, sra, sraforuse, srl, srlforuse,registers,control, check Zero, presentation and site
Farah: ALU, CPU, control, registers, presentation, site