translator.visitor.intermediateVisitor.verilogTree.standardRam
index
/home/yentl/UA/devs-eindwerk/translator/translator/visitor/intermediateVisitor/verilogTree/standardRam.py

 
Classes
       
translator.visitor.intermediateVisitor.verilogTree.ram.Ram(translator.visitor.intermediateVisitor.verilogTree.memory.Memory)
StandardRam

 
class StandardRam(translator.visitor.intermediateVisitor.verilogTree.ram.Ram)
    StandardRam corresponds to the Ram of the intermediate tree, with one synchronous or asynchronous load/store port
 
 
Method resolution order:
StandardRam
translator.visitor.intermediateVisitor.verilogTree.ram.Ram
translator.visitor.intermediateVisitor.verilogTree.memory.Memory
translator.visitor.intermediateVisitor.verilogTree.node.Node
builtins.object

Methods defined here:
__init__(self, name, hasClock, extraNames)
Constructor

Data descriptors inherited from translator.visitor.intermediateVisitor.verilogTree.node.Node:
__dict__
dictionary for instance variables (if defined)
__weakref__
list of weak references to the object (if defined)