Merge branch 'yentl' of msdl.uantwerpen.be:yentl/modelverse into yentl

model/model.py

@@ -77,6 +77,8 @@ class ModelverseState(AtomicDEVS):
                 "delete_edge": delete_edge,
             }
 
+        self.state = MvSState()
+
         self.from_mvk = self.addInPort("from_MvK")
         self.to_mvk = self.addOutPort("to_MvK")
 
@@ -109,7 +111,8 @@ class ModelverseState(AtomicDEVS):
 
 class MvKState(object):
     def __init__(self):
-        self.mvk = MvK()
+        self.mvk = None
+        self.waiting = False
 
 class ModelverseKernel(AtomicDEVS):
     def __init__(self):
@@ -127,14 +130,36 @@ class ModelverseKernel(AtomicDEVS):
             pass
         elif self.from_mvs in inputs:
             # Got input from MvS, so we can continue processing
-            pass
+            if self.state.mvk is None:
+                # No MvK, so set it with the root we have just received (or should have received)
+                self.state.mvk = MvK(inputs[self.from_mvs][0])
+
+        return self.state
+
+    def intTransition(self):
+        if self.state.mvk is None:
+            self.state.waiting = True
 
         return self.state
 
+    def outputFnc(self):
+        if self.state.mvk is None:
+            # Ask the root first
+            return {self.to_mvs: [("RR", [])]}
+
+    def timeAdvance(self):
+        if self.state.waiting:
+            return float("inf")
+        elif self.state.mvk is None:  
+            return 0
+        else:
+            return float("inf")
+
 class MvIState():
     def __init__(self):
         self.operations = []
         self.output = []
+        self.processing = []
         self.memory = {}
 
 class ModelverseInterface(AtomicDEVS):
@@ -186,20 +211,20 @@ class NetworkState(object):
         self.timer = float("inf")
 
 class Network(AtomicDEVS):  
-    def __init__(self, latency, bytes_per_second):
-        AtomicDEVS.__init__(self, "Network")
+    def __init__(self, name, latency, bandwidth):
+        AtomicDEVS.__init__(self, name)
         self.state = NetworkState()
 
         self.input_port = self.addInPort("input_port")
         self.output_port = self.addOutPort("output_port")
 
         self.latency = latency
-        self.bytes_per_second = bytes_per_second
+        self.bandwidth = bandwidth
 
     def intTransition(self):
         self.state.processing.pop(0)
         if self.state.processing:
-            self.state.timer = len(self.state.processing[0]) / self.bytes_per_second + self.latency
+            self.state.timer = int(len(self.state.processing[0]) / float(self.bandwidth) + self.latency)
         else:
             self.state.timer = float("inf")
         return self.state
@@ -269,20 +294,24 @@ class System(CoupledDEVS):
                             delete_edge         = delete_edge
                         ))
         self.mvi2mvk = self.addSubModel(Network(\
-                            mvi2mvk_latency     = mvi2mvk_latency,
-                            mvi2mvk_bandwidth   = mvi2mvk_bandwidth
+                            name        = "mvi2mvk",
+                            latency     = mvi2mvk_latency,
+                            bandwidth   = mvi2mvk_bandwidth
                         ))
         self.mvk2mvs = self.addSubModel(Network(\
-                            mvk2mvs_latency     = mvk2mvs_latency,
-                            mvk2mvs_bandwidth   = mvk2mvs_bandwidth
+                            name        = "mvk2mvs",
+                            latency     = mvk2mvs_latency,
+                            bandwidth   = mvk2mvs_bandwidth
                         ))
         self.mvs2mvk = self.addSubModel(Network(\
-                            mvs2mvk_latency     = mvs2mvk_latency,
-                            mvs2mvk_bandwidth   = mvs2mvk_bandwidth
+                            name        = "mvs2mvk",
+                            latency     = mvs2mvk_latency,
+                            bandwidth   = mvs2mvk_bandwidth
                         ))
         self.mvk2mvi = self.addSubModel(Network(\
-                            mvk2mvi_latency     = mvk2mvi_latency,
-                            mvk2mvi_bandwidth   = mvk2mvi_bandwidth
+                            name        = "mvk2mvi",
+                            latency     = mvk2mvi_latency,
+                            bandwidth   = mvk2mvi_bandwidth
                         ))
 
         self.connectPorts(self.mvi.to_mvk, self.mvi2mvk.input_port)
@@ -293,3 +322,41 @@ class System(CoupledDEVS):
         self.connectPorts(self.mvs2mvk.output_port, self.mvk.from_mvs)
         self.connectPorts(self.mvk.to_mvi, self.mvk2mvi.input_port)
         self.connectPorts(self.mvk2mvi.output_port, self.mvi.from_mvk)
+
+operations = [
+        "test",
+    ]
+
+args = {
+        "operations": operations,
+        "mvi2mvk_latency":      1,
+        "mvi2mvk_bandwidth":    2000,
+        "mvk2mvs_latency":      1,
+        "mvk2mvs_bandwidth":    2000,
+        "mvs2mvk_latency":      1,
+        "mvs2mvk_bandwidth":    2000,
+        "mvk2mvi_latency":      1,
+        "mvk2mvi_bandwidth":    2000,
+        "read_root":            lambda: 1,
+        "create_node":          lambda: 1,
+        "create_edge":          lambda: 1,
+        "create_nodevalue":     lambda: 1,
+        "create_dict":          lambda: 1,
+        "read_value":           lambda: 1,
+        "read_outgoing":        lambda: 1,
+        "read_incoming":        lambda: 1,
+        "read_edge":            lambda: 1,
+        "read_dict":            lambda: 1,
+        "read_dict_keys":       lambda: 1,
+        "read_dict_node":       lambda: 1,
+        "read_dict_edge":       lambda: 1,
+        "read_dict_node_edge":  lambda: 1,
+        "read_reverse_dict":    lambda: 1,
+        "delete_node":          lambda: 1,
+        "delete_edge":          lambda: 1,
+    }
+
+model = System(**args)
+sim = Simulator(model)
+sim.setTerminationTime(1000)
+sim.simulate()