Fixed buggy dict_eq operation (I think...)

bootstrap/model_management.alc

@@ -149,8 +149,6 @@ Void function model_join(dst_model : Element, src_model : Element, retyping_key
 	keys = dict_keys(src_model["model"])
 	while (read_nr_out(keys) > 0):
 		name = set_pop(keys)
-		log("Remaining elements: " + cast_i2s(read_nr_out(keys)))
-
 		type = read_type(src_model, name)
 
 		if (is_edge(src_model["model"][name])):
@@ -205,8 +203,6 @@ Element function model_split(src_model : Element, target_metamodel : Element, re
 	while (read_nr_out(keys) > 0):
 		name = set_pop(keys)
 
-		log("Remaining elements: " + cast_i2s(read_nr_out(keys)))
-
 		type = read_type(src_model, name)
 		if (string_startswith(type, retyping_key)):
 			new_type = string_substr(type, length, string_len(type))

kernel/modelverse_kernel/compiled.py

@@ -49,6 +49,7 @@ def read_attribute(a, b, c, **remainder):
     raise Exception("Error in reading edge!")
 """
 
+"""
 def dict_eq(a, b, **remainder):
     keys_a, keys_b = yield [("RDK", [a]), ("RDK", [b])]
     if len(keys_a) != len(keys_b):
@@ -70,6 +71,7 @@ def dict_eq(a, b, **remainder):
 
     result, = yield [("CNV", [dict_a == dict_b])]
     raise PrimitiveFinished(result)
+"""
 
 def set_copy(a, **remainder):
     b, =         yield [("CN", [])]

models/control_to_EPN.mvc

@@ -289,9 +289,6 @@ All_RAM Control2EPN {
                     label = "6"
                 }
 
-                Pre_Encapsulated_PetriNet/Place pre_ct_7 {
-                    label = "7"
-                }
                 Pre_Encapsulated_PetriNet/Port pre_ct_9 {
                     label = "9"
                     constraint_name = $
@@ -299,13 +296,13 @@ All_RAM Control2EPN {
                             return bool_or(bool_or(value == "up", value == "neutral"), value == "down")!
                         $
                 }
+                Pre_Encapsulated_PetriNet/Place pre_ct_7 {
+                    label = "7"
+                }
                 Pre_Encapsulated_PetriNet/PortPlace (pre_ct_9, pre_ct_7) {
                     label = "8"
                 }
 
-                Pre_Encapsulated_PetriNet/Place pre_ct_10 {
-                    label = "10"
-                }
                 Pre_Encapsulated_PetriNet/Port pre_ct_12 {
                     label = "12"
                     constraint_name = $
@@ -313,13 +310,13 @@ All_RAM Control2EPN {
                             return bool_or(bool_or(value == "up", value == "neutral"), value == "down")!
                         $
                 }
+                Pre_Encapsulated_PetriNet/Place pre_ct_10 {
+                    label = "10"
+                }
                 Pre_Encapsulated_PetriNet/PortPlace (pre_ct_12, pre_ct_10) {
                     label = "11"
                 }
 
-                Pre_Encapsulated_PetriNet/Place pre_ct_13 {
-                    label = "13"
-                }
                 Pre_Encapsulated_PetriNet/Port pre_ct_15 {
                     label = "15"
                     constraint_name = $
@@ -327,6 +324,9 @@ All_RAM Control2EPN {
                             return bool_or(bool_or(value == "cmdUp", value == "cmdNeutral"), value == "cmdDown")!
                         $
                 }
+                Pre_Encapsulated_PetriNet/Place pre_ct_13 {
+                    label = "13"
+                }
                 Pre_Encapsulated_PetriNet/PortPlace (pre_ct_15, pre_ct_13) {
                     label = "14"
                 }