parallel_history.xml 4.2 KB

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  1. <?xml version="1.0" ?>
  2. <diagram author="Glenn De Jonghe" name="TestParallelHistory">
  3. <description>
  4. Testing history in parallel.
  5. </description>
  6. <inport name="test_input" />
  7. <outport name="test_output" />
  8. <class name="TestClass" default="true">
  9. <scxml>
  10. <parallel id="parallel">
  11. <state id="orthogonal_1" initial="orthogonal_inner_1">
  12. <state id="orthogonal_inner_1" initial="state_1">
  13. <state id="state_1">
  14. <onentry>
  15. <raise port="test_output" event="in_state_1" />
  16. </onentry>
  17. <transition port="test_input" event="to_state_2" target="../state_2"/>
  18. </state>
  19. <state id="state_2">
  20. <onentry>
  21. <raise port="test_output" event="in_state_2" />
  22. </onentry>
  23. </state>
  24. <transition port="test_input" event="to_outer_1" target="../outer_1"/>
  25. <history id="history_1" type="shallow">
  26. <transition target="../state_1"/>
  27. </history>
  28. </state>
  29. <state id="outer_1">
  30. <onentry>
  31. <raise port="test_output" event="in_outer_1" />
  32. </onentry>
  33. <transition port="test_input" event="to_history_1" target="../orthogonal_inner_1/history_1"/>
  34. </state>
  35. </state>
  36. <state id="orthogonal_2" initial="orthogonal_inner_2">
  37. <state id="orthogonal_inner_2" initial="state_3">
  38. <state id="state_3">
  39. <onentry>
  40. <raise port="test_output" event="in_state_3" />
  41. </onentry>
  42. <transition port="test_input" event="to_state_4" target="../state_4"/>
  43. </state>
  44. <state id="state_4">
  45. <onentry>
  46. <raise port="test_output" event="in_state_4" />
  47. </onentry>
  48. </state>
  49. <transition port="test_input" event="to_outer_2" target="../outer_2"/>
  50. <history id="history_2" type="shallow">
  51. <transition target="../state_3"/>
  52. </history>
  53. </state>
  54. <state id="outer_2">
  55. <onentry>
  56. <raise port="test_output" event="in_outer_2" />
  57. </onentry>
  58. <transition port="test_input" event="to_history_2" target="../orthogonal_inner_2/history_2"/>
  59. </state>
  60. </state>
  61. </parallel>
  62. </scxml>
  63. </class>
  64. <test>
  65. <input>
  66. <event name="to_state_2" port="test_input" time="0.0"/>
  67. <event name="to_state_4" port="test_input" time="0.0"/>
  68. <event name="to_outer_1" port="test_input" time="0.0"/>
  69. <event name="to_outer_2" port="test_input" time="0.0"/>
  70. <event name="to_history_1" port="test_input" time="0.0"/>
  71. <event name="to_history_2" port="test_input" time="0.0"/>
  72. </input>
  73. <expected>
  74. <slot>
  75. <event name="in_state_1" port="test_output"/>
  76. <event name="in_state_3" port="test_output"/>
  77. </slot>
  78. <slot>
  79. <event name="in_state_2" port="test_output"/>
  80. </slot>
  81. <slot>
  82. <event name="in_state_4" port="test_output"/>
  83. </slot>
  84. <slot>
  85. <event name="in_outer_1" port="test_output"/>
  86. </slot>
  87. <slot>
  88. <event name="in_outer_2" port="test_output"/>
  89. </slot>
  90. <slot>
  91. <event name="in_state_2" port="test_output"/>
  92. </slot>
  93. <slot>
  94. <event name="in_state_4" port="test_output"/>
  95. </slot>
  96. </expected>
  97. </test>
  98. </diagram>