SCCD/test/legacy_test_files/semantics/original_semantics/parallel.xml

<?xml version="1.0" ?>
<diagram
	xmlns="msdl.uantwerpen.be/sccd"
	author="Glenn De Jonghe"
	name="TestParallel">
    <description>
        Testing parallelism.
    </description>
    <inport name="test_input" />
    <outport name="test_output" />
    <class name="Class1" default="true">
        <scxml>
            <parallel id="parallel_1">
                <state id="orthogonal_1" initial="state_1">
                    <state id="state_1">
                        <onentry>
                           <raise port="test_output" event="in_state_1" />
                        </onentry>
                        <transition port="test_input" event="to_state_2" target="../state_2"/>
                    </state>
                    <state id="state_2">
                        <onentry>
    	                   <raise port="test_output" event="in_state_2" />
                        </onentry>
                        <transition port="test_input" event="to_state_1" target="../state_1"/>
                    </state>
                </state>
                <state id="orthogonal_2" initial="state_3">
                    <state id="state_3">
                        <onentry>
                           <raise port="test_output" event="in_state_3" />
                        </onentry>
                        <transition port="test_input" event="to_state_4" target="../state_4"/>
                    </state>
                    <state id="state_4">
                        <onentry>
                           <raise port="test_output" event="in_state_4" />
                        </onentry>
                        <transition port="test_input" event="to_state_3" target="../state_3"/>
                    </state>
                 </state>
            </parallel>
        </scxml>
    </class>
    <test>
        <input>
            <event name="to_state_2" port="test_input" time="0"/>
            <event name="to_state_4" port="test_input" time="0"/>
            <event name="to_state_1" port="test_input" time="0"/>
            <event name="to_state_2" port="test_input" time="0"/>
            <event name="to_state_3" port="test_input" time="0"/>
        </input>
        <expected>
            <slot>
                <event name="in_state_1" port="test_output"/>
                <event name="in_state_3" port="test_output"/>
            </slot>
            <slot>
                <event name="in_state_2" port="test_output"/>
            </slot>
            <slot>
                <event name="in_state_4" port="test_output"/>
            </slot>
            <slot>
                <event name="in_state_1" port="test_output"/>
            </slot>
            <slot>
                <event name="in_state_2" port="test_output"/>
            </slot>
            <slot>
                <event name="in_state_3" port="test_output"/>
            </slot>
        </expected>
    </test>
</diagram>