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  1. <html>
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  3. <title>Shift Register</title>
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  5. <body bgcolor="FFFFFF">
  6. <h1><img align="center" src="../../../../en/icons/shiftreg.gif" width="32" height="32">
  7. <em>Shift Register</em></h1>
  8. <p><table>
  9. <tr><td><strong>Library:</strong></td>
  10. <td><a href="index.html">Memory</a></td></tr>
  11. <tr><td><strong>Introduced:</strong></td>
  12. <td>2.3.0</td></tr>
  13. <tr><td valign="top"><strong>Appearance:</strong></td>
  14. <td valign="top"><img src="../../../../en/img-libs/shiftreg.png" width="104" height="44"></td></tr>
  15. </table></p>
  16. <h2>Behavior</h2>
  17. <p>This register consists of several stages, where each clock may lead to
  18. each stage receiving the value in the previous stage, while a new value is
  19. loaded into the first stage. The component optionally also supports parallel
  20. loads and stores to all stages' values.</p>
  21. <p>The <var>clear</var> input resets all stages to 0 (all
  22. zeroes) asynchronously; that is, as long as the <var>clear</var> input
  23. is 1, all values are pinned to 0, regardless of the clock input.</p>
  24. <h2>Pins</h2>
  25. <p>* An asterisk marks pins that exist only when the Parallel Load attribute
  26. is enabled.</p>
  27. <dl>
  28. <dt>West edge, top pin (input, bit width 1)</dt>
  29. <dd>Shift: When 1 or disconnected, all stages advance with the clock trigger;
  30. but if it is 0, no advance takes place. This input is ignored if the Load
  31. input is 1.</dd>
  32. <dt>West edge, middle pin (input, bit width matches Data Bits attribute)</dt>
  33. <dd>Data: When advancing the stages, the value found at this input is loaded
  34. into the first stage.</dd>
  35. <dt>West edge, bottom pin marked with triangle (input, bit width 1)</dt>
  36. <dd>Clock: At the instant that this is triggered as specified by the
  37. Trigger attribute, the component may advance the stages or load new values.</dd>
  38. <dt>*North edge, left pin (input, bit width 1)</dt>
  39. <dd>Load: When this 1, the values found on the other north-edge pins are
  40. loaded into all stages at the next clock trigger. When 0 or disconnected, no
  41. load occurs.</dd>
  42. <dt>*North edge, other pins (input, bit width matches Data Bits attribute)</dt>
  43. <dd>Data: These values are loaded into all stages when the clock is triggered
  44. while the <var>load</var> input is 1. The leftmost input corresponds to the
  45. youngest stage.</dd>
  46. <dt>South edge, left pin (input, bit width 1)</dt>
  47. <dd>Clear: When this is 1, all stages are asynchronously reset to 0, and all
  48. other inputs are ignored.</dd>
  49. <dt>*South edge, other pins (output, bit width matches Data Bits attribute)</dt>
  50. <dd>Output: Emits the value stored in each stage, with the youngest stage
  51. reflected on the leftmost of the pins (next to the <var>clear</var> input).</dd>
  52. <dt>East edge (output, bit width matches Data Bits attribute)</dt>
  53. <dd>Output: Emits the value stored in the final (oldest) stage.</dd>
  54. </dl>
  55. <h2>Attributes</h2>
  56. <p>When the component is selected or being added,
  57. the digits '0' through '9' alter its <q>Number of Stages</q> attribute
  58. and Alt-0 through Alt-9 alter its <q>Data Bits</q> attribute.</p>
  59. <dl>
  60. <dt>Data Bits</dt>
  61. <dd>The bit width of the value stored in each stage.</dd>
  62. <dt>Number of Stages</dt>
  63. <dd>The number of stages included in the component.</dd>
  64. <dt>Parallel Load</dt>
  65. <dd>If <q>yes,</q> then the component includes inputs and outputs facilitating
  66. parallel access to all the stages' values.</dd>
  67. <dt>Trigger</dt>
  68. <dd>Configures how the clock input is interpreted. The value <q>rising edge</q>
  69. indicates that the register should update its value at the instant when the
  70. clock rises from 0 to 1. The <q>falling edge</q> value indicates that it should
  71. update at the instant the clock falls from 1 to 0.</dd>
  72. <dt>Label</dt>
  73. <dd>The text within the label associated with the component.</dd>
  74. <dt>Label Font</dt>
  75. <dd>The font with which to render the label.</dd>
  76. </dl>
  77. <h2>Poke Tool Behavior</h2>
  78. <p>If the Parallel Load attribute is no, or if the Data Bits attribute is more
  79. than 4, then poking the register has no effect. Otherwise, clicking the
  80. component will bring keyboard focus to the clicked stage
  81. (indicated by a red rectangle), and typing a hexadecimal digit will
  82. change the value stored in that stage.</p>
  83. <h2>Text Tool Behavior</h2>
  84. <p>Allows the label associated with the component to be edited.</p>
  85. <p><a href="../index.html">Back to <em>Library Reference</em></a></p>
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