ram.html 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156
  1. <html>
  2. <head>
  3. <title>RAM</title>
  4. </head>
  5. <body bgcolor="FFFFFF">
  6. <h1><img align="center" src="../../../icons/ram.gif" width="32" height="32">
  7. <em>RAM</em></h1>
  8. <p><table>
  9. <tr><td><strong>Library:</strong></td>
  10. <td><a href="index.html">Memory</a></td></tr>
  11. <tr><td><strong>Introduced:</strong></td>
  12. <td>2.0 Beta 1</td></tr>
  13. <tr><td valign="top"><strong>Appearance:</strong></td>
  14. <td valign="top"><img src="../../../img-libs/ram.png" width="305" height="84"></td></tr>
  15. </table></p>
  16. <h2>Behavior</h2>
  17. <p>The RAM component, easily the most complex component in Logisim's
  18. built-in libraries, stores up to 16,777,216 values (specified in the Address
  19. Bit Width attribute), each of which can include up to to 32 bits
  20. (specified in the Data Bit Width attribute). The circuit can load and
  21. store values in RAM. Also, the user can modify individual values
  22. interactively via the Poke Tool, or the user can modify the entire
  23. contents via the Menu Tool.</p>
  24. <p>Current values are displayed in the component. Addresses displayed
  25. are listed in gray to the left of the display area. Inside, each value
  26. is listed using hexadecimal. The value at the currently selected address
  27. will be displayed in inverse text (white on black).</p>
  28. <p>The RAM component supports three different interfaces, depending on the
  29. Data Interface attribute.</p>
  30. <dl>
  31. <dt>One synchronous load/store port (default)</dt>
  32. <dd><p>The component includes a single port on its east side that serves for both
  33. loading and storing data. Which it performs depends on the input labeled
  34. <em>ld</em>: 1 (or floating) indicates to load the data at the address
  35. designated on the component's west side, and 0 indicates to store the data
  36. given on the port. To transmit data into and out of the component, you will
  37. need to use a Controlled Buffer component, as illustrated below.</p>
  38. <center><img src="../../../img-libs/ramdemo.png" width="384" height="159"></center></dd>
  39. <dt>One asynchronous load/store port</dt>
  40. <dd><p>This is the same as above, except that there is no clock. The value
  41. found on the data bus is stored into memory whenever the <em>ld</em> input is
  42. 0. If, while the <em>ld</em> input is 0, the address or data changes, then an
  43. additional store occurs. This option is meant to more closely approximate the
  44. interface of many available random-access memories.</p></dd>
  45. <dt>Separate load and store ports</dt>
  46. <dd><p>Two data ports are provided - one on the west side for storing data,
  47. and another on the east side for loading data. This option removes the
  48. necessity of dealing with the Controlled Buffer and so it is easier to
  49. use.</p></dd>
  50. <h2>Pins</h2>
  51. <dl>
  52. <dt><var>A</var> on west edge (input, bit width matches Address Bit Width attribute)</dt>
  53. <dd>Selects which of the values in memory is currently being accessed by the
  54. circuit.</dd>
  55. <dt><var>D</var> on west edge (input, bit width matches Data Bit Width attribute)</dt>
  56. <dd>This input is present only if "separate load and store ports" is selected
  57. for the Data Interface attribute. When a store is requested (via the clock changing
  58. from 0 to 1 while <em>sel</em> and <em>str</em> are both 1 or floating), the
  59. value found at this port is stored into memory at the currently selected address.</dd>
  60. <dt><var>D</var> on east edge (input/output or output, bit width matches Data Bit Width attribute)</dt>
  61. <dd>If <var>sel</var> and <var>ld</var> are 1 or floating, then the RAM
  62. component emits the value found at the currently selected address on this port.
  63. If there is a single load/store port, the value read from this port is
  64. stored whenever a store is requested.</dd>
  65. <dt><var>str</var> on south edge (input, bit width 1)</dt>
  66. <dd>Store: This input is present only if "separate load and store ports" is selected
  67. for the Data Interface attribute. When it is 1 or floating, a clock pulse will result
  68. in storing the data found on the west edge into memory (provided the
  69. <var>sel</var> input is also 1 or floating).</dd>
  70. <dt><var>sel</var> on south edge (input, bit width 1)
  71. <dd>Chip select: This input enables or disables the entire RAM module, based on
  72. whether the value is 1/floating or 0. The input is meant primarily for
  73. situations where you have multiple RAM units, only one of which would be
  74. enabled at any time.</dd>
  75. <dt>triangle on south edge (input, bit width 1)
  76. <dd>Clock input: This is absent when the Data Interface attribute's value is "One
  77. asynchronous load/store port." In other circumstances, when <var>ld</var> is 0,
  78. and this input rises from 0 to 1 (and <var>sel</var> is 1/undefined and
  79. <var>clr</var> is 0), then the value at the currently selected address
  80. changes to whatever value is
  81. at the <var>D</var> pin. As long as the clock input remains 0 or 1,
  82. though, the <var>D</var> value will not be stored into memory.</dd>
  83. <dt><var>ld</var> on south edge (input, bit width 1)
  84. <dd>Load: Selects whether the RAM should emit (on <var>D</var>)
  85. the value at the current address (<var>A</var>). This output behavior
  86. is enabled if <var>out</var> is 1 or undefined; if <var>out</var>
  87. is 0, then no value is pushed onto <var>D</var> - but if there is a combined
  88. load/store port, stores will be enabled.</dd>
  89. <dt><var>clr</var> on south edge (input, bit width 1)</dt>
  90. <dd>Clear: When this is 1, all values
  91. in memory are pinned to 0, no matter what the other inputs are.</dd>
  92. </dl>
  93. <h2>Attributes</h2>
  94. <p>When the component is selected or being added,
  95. the digits '0' through '9' alter its <q>Address Bit Width</q> attribute
  96. and Alt-0 through Alt-9 alter its <q>Data Bit Width</q> attribute.</p>
  97. <dl>
  98. <dt>Address Bit Width</dt>
  99. <dd>The bit width of the address bits. The number of values stored in
  100. RAM is 2<sup><var>addrBitWidth</var></sup>.</dd>
  101. <dt>Data Bit Width</dt>
  102. <dd>The bit width of each individual value in memory.</dd>
  103. <dt>Data Interface</dt>
  104. <dd>Configures which of the three interfaces are used for communicating data
  105. into and out of the component.</dd>
  106. </dl>
  107. <h2>Poke Tool Behavior</h2>
  108. <p>See <a href="../../guide/mem/poke.html">poking memory</a>
  109. in the <em>User's Guide</em>.</p>
  110. <h2>Text Tool Behavior</h2>
  111. <p>None.</p>
  112. <h2>Menu Tool Behavior</h2>
  113. <p>See <a href="../../guide/mem/menu.html">pop-up menus and files</a>
  114. in the <em>User's Guide</em>.</p>
  115. <p><a href="../index.html">Back to <em>Library Reference</em></a></p>
  116. </body>
  117. </html>